1. Field of the Invention
The present invention relates to an article of manufacture and apparatus for planarizing a substrate surface.
2. Background of the Related Art
Sub-quarter micron multi-level metallization is one of the key technologies for the next generation of ultra large-scale integration (ULSI). The multilevel interconnects that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, lines and other features. Reliable formation of these interconnect features is very important to the success of ULSI and to the continued effort to increase circuit density and quality on individual substrates and die.
In the fabrication of integrated circuits and other electronic devices, multiple layers of conducting, semiconducting, and dielectric materials are deposited on or removed from a surface of a substrate. Thin layers of conducting, semiconducting, and dielectric materials may be deposited by a number of deposition techniques. Common deposition techniques in modern processing include physical vapor deposition (PVD), also known as sputtering, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and electro-chemical plating (ECP). chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and electrochemical plating (ECP).
As layers of materials are sequentially deposited and removed, the uppermost surface of the substrate may become non-planar across its surface and require planarization. Planarizing a surface, or “polishing” a surface, is a process where material is removed from the surface of the substrate to form a generally even, planar surface. Planarization is useful in removing undesired surface topography and surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials. Planarization is also useful in forming features on a substrate by removing excess deposited material used to fill the features and to provide an even surface for subsequent levels of metallization and processing.
Chemical mechanical planarization, or chemical mechanical polishing (CMP), is a common technique used to planarize substrates. CMP utilizes a chemical composition, typically a slurry or other fluid medium, for selective removal of material from substrates. In conventional CMP techniques, a substrate carrier or polishing head is mounted on a carrier assembly and positioned in contact with a polishing pad in a CMP apparatus. The carrier assembly provides a controllable pressure to the substrate urging the substrate against the polishing pad. The pad is moved relative to the substrate by an external driving force. The CMP apparatus effects polishing or rubbing movement between the surface of the substrate and the polishing pad while dispersing a polishing composition to effect chemical activity and/or mechanical activity and consequential removal of material from the surface of the substrate
One material increasingly utilized in integrated circuit fabrication is copper due to its desirable electrical properties. However, copper has its own special fabrication problems. For example, copper is difficult to pattern and etch and new processes and techniques, such as damascene or dual damascene processes, are being used to form copper substrate features. In damascene processes, a feature is defined in a dielectric material and subsequently filled with copper. Dielectric materials with low dielectric constants, i.e., less than about 3, are being used in the manufacture of copper damascenes. Barrier layer materials are deposited conformally on the surfaces of the features formed in the dielectric layer prior to deposition of copper material. Copper material is then deposited over the barrier layer and the surrounding field. However, copper fill of the features usually results in excess copper material, or overburden, on the substrate surface that must be removed to form a copper filled feature in the dielectric material and prepare the substrate surface for subsequent processing.
One challenge that is presented in polishing copper materials is that the interface between the conductive material and the barrier layer is generally non-planar and residual copper material is retained in irregularities formed by the non-planar interface. Further, the conductive material and the barrier materials are often removed from the substrate surface at different rates, both of which can result in excess conductive material being retained as residues on the substrate surface. Additionally, the substrate surface may have different surface topography, depending on the density or size of features formed therein. Copper material is removed at different removal rates along the different surface topography of the substrate surface, which makes effective removal of copper material from the substrate surface and final planarity of the substrate surface difficult to achieve.
One solution to remove all of the desired copper material from the substrate surface is to overpolish the substrate surface. However, overpolishing of some materials can result in the formation of topographical defects, such as concavities or depressions in features, referred to as dishing, or excessive removal of dielectric material, referred to as erosion. The topographical defects from dishing and erosion can further lead to non-uniform removal of additional materials, such as barrier layer materials disposed thereunder, and produce a substrate surface having a less than desirable polishing quality.
Another problem with the polishing of copper surfaces arises from the use of low dielectric constant (low k) dielectric materials to form copper damascenes in the substrate surface. Low k dielectric materials, such as carbon doped silicon oxides, may deform or fracture under conventional polishing pressures (i.e., about 6 psi), called downforce, which can detrimentally affect substrate polish quality and detrimentally affect device formation. For example, relative rotational movement between the substrate and a polishing pad can induce a shear force along the substrate surface and deform the low k material to form topographical defects, which can detrimentally affect subsequent polishing.
One solution for polishing copper in low dielectric materials with reduced or minimal defects formed thereon is by polishing copper by electrochemical mechanical polishing (ECMP) techniques. ECMP techniques remove conductive material from a substrate surface by electrochemical dissolution while concurrently polishing the substrate with reduced mechanical abrasion compared to conventional CMP processes. The electrochemical dissolution is performed by applying a bias between a cathode and substrate surface to remove conductive materials from a substrate surface into a surrounding electrolyte. In one embodiment of an ECMP system, the bias is applied by a ring of conductive contacts in electrical communication with the substrate surface in a substrate support device, such as a substrate carrier head. However, the contact ring has been observed to exhibit non-uniform distribution of current over the substrate surface, which results in non-uniform dissolution. Mechanical abrasion is performed by positioning the substrate in contact with conventional polishing pads and providing relative motion therebetween. However, conventional polishing pads often limit electrolyte flow to the surface of the substrate. Additionally, the polishing pad may be composed of insulative materials that may interfere with the application of bias to the substrate surface and result in non-uniform or variable dissolution of material from the substrate surface.
As a result, there is a need for an improved polishing article for the removal of conductive material on a substrate surface.